JPH0460348B2 - - Google Patents

Info

Publication number
JPH0460348B2
JPH0460348B2 JP24794484A JP24794484A JPH0460348B2 JP H0460348 B2 JPH0460348 B2 JP H0460348B2 JP 24794484 A JP24794484 A JP 24794484A JP 24794484 A JP24794484 A JP 24794484A JP H0460348 B2 JPH0460348 B2 JP H0460348B2
Authority
JP
Japan
Prior art keywords
solder
connection layer
cap
sealing
inward
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP24794484A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61127150A (ja
Inventor
Yoshuki Ishii
Toshikatsu Kiryama
Tokio Sakate
Ichiro Oohigata
Akira Ito
Kazumasa Arai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP24794484A priority Critical patent/JPS61127150A/ja
Publication of JPS61127150A publication Critical patent/JPS61127150A/ja
Publication of JPH0460348B2 publication Critical patent/JPH0460348B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/15165Monolayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Wire Bonding (AREA)
JP24794484A 1984-11-26 1984-11-26 半導体パツケ−ジの封止構造 Granted JPS61127150A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24794484A JPS61127150A (ja) 1984-11-26 1984-11-26 半導体パツケ−ジの封止構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24794484A JPS61127150A (ja) 1984-11-26 1984-11-26 半導体パツケ−ジの封止構造

Publications (2)

Publication Number Publication Date
JPS61127150A JPS61127150A (ja) 1986-06-14
JPH0460348B2 true JPH0460348B2 (en]) 1992-09-25

Family

ID=17170868

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24794484A Granted JPS61127150A (ja) 1984-11-26 1984-11-26 半導体パツケ−ジの封止構造

Country Status (1)

Country Link
JP (1) JPS61127150A (en])

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101602278B1 (ko) * 2015-09-11 2016-03-10 주식회사 피플앤코 자력퍼프 및 자력퍼프 손잡이 돌출형 화장품 콤팩트

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0649700A (ja) * 1992-07-31 1994-02-22 Sumitomo Metal Ind Ltd 帯鋼連続酸洗装置
JP4513513B2 (ja) * 2004-11-09 2010-07-28 株式会社村田製作所 電子部品の製造方法
FR2949172B1 (fr) * 2009-08-13 2011-08-26 Commissariat Energie Atomique Assemblage hermetique de deux composants et procede de realisation d'un tel assemblage

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101602278B1 (ko) * 2015-09-11 2016-03-10 주식회사 피플앤코 자력퍼프 및 자력퍼프 손잡이 돌출형 화장품 콤팩트

Also Published As

Publication number Publication date
JPS61127150A (ja) 1986-06-14

Similar Documents

Publication Publication Date Title
US6002172A (en) Substrate structure and method for improving attachment reliability of semiconductor chips and modules
US4626960A (en) Semiconductor device having soldered bond between base and cap thereof
US5705858A (en) Packaging structure for a hermetically sealed flip chip semiconductor device
JP3576727B2 (ja) 表面実装型パッケージ
JP2570628B2 (ja) 半導体パッケージおよびその製造方法
JP3420076B2 (ja) フリップチップ実装基板の製造方法及びフリップチップ実装基板及びフリップチップ実装構造
US4839716A (en) Semiconductor packaging
WO2008055105A2 (en) Non-pull back pad package with an additional solder standoff
US6501160B1 (en) Semiconductor device and a method of manufacturing the same and a mount structure
KR101146973B1 (ko) 패키지 프레임 및 그를 이용한 반도체 패키지
JPS62149155A (ja) 封止電子装置
KR20060136262A (ko) 패키지 프레임 및 그를 이용한 반도체 패키지
JPH0460348B2 (en])
JPS5917271A (ja) セラミツクパツケ−ジ半導体装置
JPH07122827A (ja) 電子部品実装用基板
JPH06140523A (ja) 半導体素子収納用パッケージ
JPH09205113A (ja) 半導体装置、実装基板及び実装構造体
JPS5824446Y2 (ja) 半導体装置
JPS62108546A (ja) 半導体パツケ−ジの封止構造
JPS6129155A (ja) 半導体装置
JPH08213503A (ja) セラミック製パッケージ及び該パッケージの封着方法
JPS634350B2 (en])
JP2001144127A (ja) はんだ接続部構造、bga型半導体パッケージの実装構造、はんだペースト、bga型半導体パッケージの電極形成プロセスおよびbga型半導体パッケージの実装プロセス
JPH02288255A (ja) 半導体装置
JPH05243415A (ja) 配線基板